In the electronic arts it is often desired to perform a unary exclusive OR (XOR) process on N parallel input bits together with a data input bit. This processing of N+1 bits is done by combining N two-bit exclusive OR gates in a suitable manner. One can choose between a complicated and fast circuit or a simple circuit which needs up to N unit propagation delays and therefore is very slow.
FIG. 1 illustrates prior art multi-bit XOR 10 comprising N two-bit XORs 12 arranged in a tree structure. N parallel input bits 14 are XORed in pairs in N/2 two-bit XORs 12 which form a first group acting in parallel. The output bits of this first group are fed to a second group acting in parallel, and so on. The last (Nth) XOR 16 in the propagation flow direction performs an XOR operation with result 18 of all N parallel input bits and the data input bit. Its output is the desired multi-bit XOR result.
The advantage of this tree structure is a short propagation delay, since the number of stages in the propagation path is log.sub.2 N. The disadvantage is that the interconnections are complex making it less suitable for VLSI implementation.
FIG. 2 shows prior art multi-bit XOR 20 with N two-bit XORs 12' arranged in a line. Similar reference numbers (12, 12') are used to identify the like or analogous elements. N parallel input bits 14 are XORed serially with the data input. It is said that the data input bit ripples through N stages.
The advantage of this serial structure is that its modularity and simple connectivity makes it very suitable for VLSI implementation. The disadvantage is the very long propagation delay of N serial stages.